Floating body effect in indium–gallium–zinc–oxide (IGZO) thin-film transistor (TFT)

In this paper, the floating body effect (FBE) in indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) and the mechanism of device failure caused by that are reported for the first time. If the toggle AC pulses are applied to the gate and drain simultaneously for the switching operation, the drain current of IGZO TFT increases dramatically and cannot show the on/off switching characteristics. This phenomenon was not reported before, and our study reveals that the main cause is the formation of a conductive path between the source and drain: short failure. It is attributed in part to the donor creation at the drain region during the high voltage (Vhigh) condition and in part to the donor creation at the source region during the falling edge and low voltage (Vlow) conditions. Donor creation is attributed to the peroxide formation in the IGZO layer induced by the electrons under the high lateral field. Because the donor creation features positive charges, it lowers the threshold voltage of IGZO TFT. In detail, during the Vhigh condition, the donor creation is generated by accumulated electrons with a high lateral field at the drain region. On the other hand, the floating electrons remaining at the short falling edge (i.e., FBE of the IGZO TFT) are affected by the high lateral field at the source region during the Vlow condition. As a result, the donor creation is generated at the source region. Therefore, the short failure occurs because the donor creations are generated and expanded to channel from the drain and source region as the AC stress accumulates. In summary, the FBE in IGZO TFT is reported, and its effect on the electrical characteristics of IGZO TFT (i.e., the short failure) is rigorously analyzed for the first time.

In this study, the floating body effect (FBE) in IGZO TFT and device failure due to FBE are reported for the first time.In addition, the mechanism and physics are compared with the FBE in silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) [22][23][24] .In the case of n-channel SOI MOSFET, the electron-hole pairs (EHPs) are generated by impact ionization as the high electric field is induced at channeldrain junction during the saturation mode [i.e., the high gate voltage (V GS ) and drain voltage (V DS )].The electrons can move toward the drain electrode while the holes are accumulated at the floating body.The accumulated holes increase the body potential, which lowers the threshold voltage (V th ) and increases the drain current (I D ).Therefore, the stored holes at the floating body cause the degradation of the device and/or circuit reliability, such as the history effect, propagation delay, and so on [22][23][24][25][26][27] .
On the other hand, it is well known that FBE rarely occurs in the IGZO TFT because it features intrinsic n-type and low impact ionization generation rate due to a large bandgap (E g > 3 eV) [28][29][30] .However, the IGZO TFT is mainly used for the gate driver in display applications, which requires a higher supply voltage than CMOS logic.Furthermore, it is vulnerable to FBE regarding circuit topology because the driver usually uses a gateddiode structure (i.e., synchronized gate and drain) [31][32][33][34] .
In this study, the FBE in IGZO TFT, which occurs when the AC pulse is applied for gated-diode operation, is reported for the first time, and the mechanism is analyzed.This paper is organized as follows.First, the fabricated device structure and measurement method are explained.Next, the electrical characteristics of IGZO TFTs are demonstrated, and their degradation mechanism due to FBE is proposed.After the mechanism is examined by the technology computer-aided design (TCAD) simulation, the FBE in IGZO TFT is compared with that in SOI MOSFET for precise analysis.

Device fabrication and measurement method
Figure 1a shows the schematic of the IGZO TFT with a self-aligned top gate structure.The channel length and width were 6 and 250 µm, respectively.After depositing a 300 nm-thick SiO 2 buffer layer on the glass substrate by using plasma-enhanced chemical vapor deposition (PECVD), a 30 nm-thick amorphous IGZO channel (In:Ga:Zn = 1:1:1 mol%) was deposited by DC sputtering.The 150 nm-thick SiO 2 gate oxide and Cu/MoTi gate were deposited by PECVD and DC sputtering, respectively.After gate patterning, the plasma treatment was performed for the highly conductive source/drain region 35 .Subsequently, the interlayer dielectric (ILD) was deposited and patterned for the source/drain region.The source/drain electrodes were formed by Cu/MoTi.
The gated diode (i.e., synchronized gate and drain) IGZO TFT is usually used as a switching device in the gate driver circuit and transmits the image signal to the pixel circuit.Therefore, the electrical characteristics were investigated after applying toggle pulses to examine the switching application.As shown in Fig. 1b, the switching pulses were composed of 12.7 V-high voltage (V high ) and − 30 V-low voltage (V low ) and applied to the gate and drain simultaneously (Fig. 1a).In addition, the pulse was set to 16.6% duty cycle with 30 ms period (i.e., the pulse with 5 ms of V high and 25 ms of V low ) and 100 ns of rising/falling time.

Electrical characteristics and degradation mechanism of IGZO TFT with AC pulse
Figure 2a shows the drain current (I D ) under the AC pulse stress in Fig. 1b.Because a period of pulse is 30 ms, the stress time 20 s (t 1 ), 40 s (t 2 ), and 60 s (t 3 ) are corresponded to 666, 1333, and 2000 pulse stress, respectively.As the stress time increases, the I D increases gradually.It is attributed to the decrease of V th (Fig. 2b).Generally, these phenomena can be explained by the donor creation at the channel adjacent to the drain region 11,12,36 .The origin of donor creation in IGZO is well known as the formation of peroxide (i.e., O 2− + O 2− → O 2 2− + 2e − ) when the strong electric field is applied to the large amount of electrons 19,20 .In detail, if the IGZO TFT is fully turned on (i.e., strong accumulation at V GS = V high ) and large V DS is applied, the high lateral electric field is applied at the channel-drain junction with high electron concentration at the channel.It can be confirmed that the extracted subgap density-of-state (DOS) [g(e)] increases after stress, corresponding to the generation of donor creation, as shown in Figure S1.As a result, there are donor creations, and the increment of carrier concentration lowers V th .
The interesting point is that the I D rapidly increases to the compliance current after 45 s (Fig. 2a) and cannot show on/off switching characteristics (Fig. 2b, t 3 ).The detailed images for the short failure are described in the supplementary information (including Figure S2).It is analyzed by the short failure between the source and drain, not the gate leakage current (Figure S3).However, the short failure cannot be explained by the abovementioned donor creation because it is locally generated at the channel adjacent to the drain.In addition, the degradation is affected by the amplitude of V low , as shown in Fig. 2a, c, and d.In detail, the short failure occurs after 45 s and 200 s with − 30 V and − 20 V-V low , respectively, while there is no failure with − 10 V-V low until 500 s stress time.In other words, the required number of stress pulses (i.e., the stress time) is increased with the smaller V low .However, the result cannot be explained by the donor creation at the drain region because the electric field at the drain is rarely affected by the amplitude of V low .Therefore, a novel degradation mechanism is needed to explain these phenomena: short failure and its dependence on V low .Our group hypothesizes that there are different degradation mechanisms depending on the segment of AC pulse applied to the gate and drain simultaneously (Fig. 3).First, in the case of V high (Fig. 3a), the electrons at the channel are affected by a high lateral electric field, especially around the drain region due to the large V DS .As a result, the donor creation occurs at the drain region, as discussed before.Second, a number of accumulated electrons remains without recombination during the 100 ns falling edge (i.e., the transition from V high to V low ) because the lifetime of electrons in IGZO is ~ μs [37][38][39] .At the same time, the electric field at the source is significantly increased when the applied voltage decreases from 0 V to V low .As a result, the donor creation occurs at the source region since the remaining electrons at the floating body are affected by the strong lateral electric field at the source region.This phenomenon (i.e., the donor creation at the source during the falling edge) is defined as the FBE in IGZO TFT and analyzed in detail (will be discussed later).Third, in the V low condition (Fig. 3c), although the lateral electric field is high enough, there is no donor creation because most of the electrons are recombined.Similarly, there are not enough electrons during the rising edge (i.e., the transition from V  www.nature.com/scientificreports/V high ) for the donor creation (Fig. 3d).In summary, if the gated-diode operation is repeated (i.e., synchronized AC pulses are applied to the gate and drain repeatedly), the donor creation occurs at the drain during the V high condition due to the accumulated electrons.In contrast, the FBE-induced donor creation occurs at the source during the falling edge due to the floating electrons.
Figure 4 shows the short failure steps in IGZO TFT (Fig. 2b, t 3 ) according to the number of the applied AC pulses.As mentioned above, the donor creation is generated at the drain and source during V high (Fig. 3a) and falling edge (Fig. 3b), respectively.Moreover, the donor creation is accumulated as the number of AC pulses increases.In the early stage of stress (Fig. 4b), the V th is decreased due to the increase of channel potential (Fig. 2b, t 1 ).As the number of applied pulses increases, the donor creation region gradually expands from the drain and source to the channel, resulting in a decrease in the effective channel length (Fig. 4c).Finally, as shown in Fig. 4d, the donor creation occurs in most channel regions.It results in short failure (channel cannot be OFF despite V low ), and the switching application of IGZO TFT is impossible (Fig. 2a and b, t 4 ).It is clear that the phenomena, which cannot be explained by the donor creation at the drain region, can be well explained by the proposed FBE-induced donor creation (for evidence of the generation of the donor creation at the drain/source region and the short failure, see the Supplementary Information, Figure S4).The critical point of the proposed degradation mechanism is that the electrons cannot be recombined during the falling edge (i.e., the FBE in IGZO TFT).

TCAD simulation of the FBE in IGZO TFT
The mixed-mode TCAD simulation is performed to verify the proposed degradation mechanism, the FBE in IGZO TFT.The parameter of DOS is extracted and adapted to the IGZO layer for precise simulation (Table S1).More details about the TCAD simulation are described in the supplementary.The AC pulse is set as in Fig. 5a, and the distribution of electron concentration and electric field along the channel are extracted at V high , V low , falling, and rising edges.The falling and rising edges are defined when the AC pulse is − 4 V as shown in the gray dot line in Fig. 5a.As shown in Fig. 5b, the electron concentration at the falling edge and at the rising edge, the former is much larger than the latter.In other words, it is confirmed a large number of floating electrons remain without recombination during the falling edge.At the same time, Fig. 5c shows the electric field at the source region is significant in order of the V low , falling/rising edges, and V high .As a result, during the falling edge, the floating electrons at the channel are affected by the high lateral electric field, generating the donor creation at the channel adjacent to the source region.Furthermore, the inset of Fig. 5c shows that the electric field decreases as the V low lowers, which is well corresponds to the tendency of short failure with the various amplitudes of the V low (Fig. 2a,c, and d).In conclusion, the short failure in IGZO TFT is attributed in part to the donor creation at the drain region during V high and in part to the FBE-induced donor creation at the source region during the falling edge.

Comparison between the FBEs in IGZO TFT and SOI MOSFET
In this section, the FBEs in IGZO TFT and SOI MOSFET are compared for precise analysis.Figure 6a shows the schematics of V GS , V DS , I D , and electron concentration of IGZO TFT with the initial and subsequent AC pulses.
As discussed in the previous section, the FBE-induced donor creation can be generated if the high lateral electric field is applied to the floating electrons, which are generated at V GS = V DS = V high and cannot be recombined during the falling edge because their lifetime is more prolonged than V high to V low transition time (Fig. 6b; FBE in IGZO TFT).Therefore, the transient time from V high to V low at the falling edge and the amplitude of the V low (i.e., lateral electric field) are the most significant factors for FBE in IGZO TFT.In the case of short t f (green line), there is donor creation because the floating electrons are affected by the high lateral electric field (Fig. 6c).
The donor creation makes V th decrease (Fig. 2b), and hence, the I D during the following pulse is more significant than that for the initial pulse.As a result, more floating electrons are generated/accumulated in the channel, and FBE is accelerated.On the contrary, if the falling edge time (t f ) is longer than the electron lifetime (indigo line, Fig. 6d), the FBE-induced donor creation cannot be generated because most of the electrons are recombined, and hence, there are not enough electrons when the source lateral electric field is increased (i.e., V GS and V DS change from 0 V to V low ; t f,low ).Therefore, it shows the same results for the initial and following pulses regarding I D and electron concentration.
On the other hand, as shown in Fig. 7a, the FBE in SOI MOSFET is defined as the decrease of V th due to the accumulated holes at the floating body in the saturation operation (i.e., V high ).Compared with FBE in IGZO TFT, the accumulation of carriers in the floating body is very similar (Fig. 7b).However, unlike the IGZO TFT, the accumulated holes in SOI MOSFET directly influence the device performance, V th shift.Therefore, the FBE is more affected by the delay time (t d ; the time between the initial pulse and the following pulse), which determines the recombination rate of the floating holes rather than t f .In the case of short t d (green line, Fig. 7c), the overdrive voltage (i.e., V GS -V th ) increases during the following pulse since the floating holes lower V th .As a result, despite the same bias condition, the larger I D generates larger excess holes due to impact ionization, and there is positive feedback regarding I D and floating holes.In contrast, if t d is longer than the lifetime of floating holes (indigo line, Fig. 7d), the SOI MOSFET under the following pulse is in the same state as that under the initial pulse because all floating holes are recombined.
Consequently, the FBEs in IGZO TFT and SOI MOSFET are similar because the accumulated carriers in the floating body influence the following pulse in both cases.However, there are main differences in terms of the way that the floating carriers impact the device characteristics.In detail, the floating electrons in IGZO TFT induce the donor creation if there is a sufficient lateral electric field.At the same time, the floating holes directly change body potential and V th in SOI MOSFET.Therefore, the dominant factors for FBEs are t d in SOI MOSFET and t f in IGZO TFT, respectively.It is noteworthy that the energy bandgap of IGZO is about three times larger than that of Si.Therefore, there are a tiny number of holes in IGZO, and the electron lifetime is much longer than that for Si.In addition, the FBE in SOI MOSFET can be suppressed by adjusting the doping concentration and by using trap engineering [40][41][42][43][44] .However, in the case of IGZO TFT, only a limited range of doping concentration is allowed 45,46 , and trap engineering is complex to use due to the amorphous active film structure 47,48 .In conclusion, even though IGZO TFT is more robust than SOI MOSFET in impact ionization, it can be more vulnerable to FBE depending on circuit operating conditions and results in short failure.

Conclusion
In this study, the FBE in IGZO TFT is reported for the first time, and the effect on the device characteristics is investigated.If the AC pulse is applied to the gate and drain simultaneously for switching operation, the donor creation at drain region during the V high condition and the FBE-induced donor creation at the source region should be considered during the falling edge.In detail, the floating electrons at the channel adjacent to the source region are accelerated and activate the peroxide formation if the transition time from V high to V low is fast enough.Therefore, the short failure occurs as the AC pulse is applied to the gated diode IGZO TFT (i.e., synchronized gate and drain) because the donor creation at the drain and source regions are generated simultaneously and expanded to the channel.Therefore, the FBE reported for the first time in this manuscript must be considered for reliable signal transmission between the gate driver circuits and pixel circuits.

Figure 1 .
Figure 1.Schematics of (a) IGZO TFT and (b) synchronized gate and drain AC pulse.

Figure 2 .
Figure 2. (a) Transient response of drain current (I D ) under the AC stress shown in Fig. 1b (i.e., V high = 12.7 V and V low = − 30 V).Here, the high level and low level current are measured during V high and V low , respectively.(b) Transfer curves before and after AC stress pulses are applied to the IGZO TFT.Transient response of I D under the AC stress with the different V low from (a); (c) V low = − 20 V and (d) V low = − 10 V.

Figure 3 .
Figure 3. Degradation mechanism of IGZO TFT during AC pulse stress under (a) V high , (b) falling edge, (c) V low , and (d) rising edge conditions.

Figure 4 .Figure 5 .
Figure 4. Schematic of short fail mechanism during ac stress with (a) initial condition and after (b) t 1 , (c) t 2 , and (d) t 3 in Fig. 2a.

3 )Figure 6 .
Figure 6.The schematics of (a) bias condition (V GS and V DS ), I D , and electron concentration of IGZO TFT with initial pulse and the next pulse applied with short falling time (green line) and long falling time (indigo line), (b) FBE in IGZO TFT at the t 1 (i.e., V GS and V DS change from V high to 0 V; t f,high ) which occurs regardless of falling time.The schematics of IGZO TFT during the (c) short falling time (t 2 ) and (d) long falling time (t 3 ).

t 2 t 3 Figure 7 .
Figure 7.The schematics of (a) bias condition (V GS and V DS ), I D , and hole concentration of SOI MOSFET with the initial pulse and the next pulse applied with short delay time (green line) and long delay time (indigo line), (b) FBE in SOI MOSFET at the t 1 which occurs regardless of delay time.The schematics of SOI MOSFET during the (c) short delay time (t 2 ) and (d) long delay time (t 3 ).